A modern application specific integrated circuit (ASIC) must meet very stringent design and performance specifications. An ASIC, or any integrated circuit, generally comprises the placement and connection of various circuit elements and structures. The complexity of a modern ASIC dictates that the circuit design be performed at different hierarchical levels because the complexity prevents a single database from containing all aspects of the design. As an example, an ASIC design can be divided into different levels, with the connections between and among levels occurring by analyzing and processing different databases having the different connections. The process of laying out circuit elements is often referred to as “floor planning” because it comprises the operation of minimizing the space used for the circuit elements. To expedite the circuit design process, abstract models of circuit elements, also referred to as “sub chips” or “circuit blocks” or “block instances” are created to allow higher level circuit routing to occur on the circuit blocks without necessarily completing the design of each block. Each “sub chip” or “circuit block” may include logic, memory, or other circuit elements.
The process of standard IC floor planning involves manually placing block instances of circuit elements based on the desired connectivity of those elements, and the placement of registers based on the desired connectivity, route factors, and timing budgets. Initial register placement can be determined automatically based on circuit block placement, or can more accurately be determined by manual process based on circuit block placement, route type and timing budgets. Both the automatic and manual processes have advantages and drawbacks. For example, automatic register placement is quicker, but less accurate than manual placement. Manual register placement is slower and more error prone, but is ultimately more accurate. In both instances, when timing data is available, the register placement is manually adjusted to verify that all timing constraints are met. This manual adjustment to register location is time consuming, error prone, and is an inefficient use of engineering resources.
Therefore, it would be desirable to have a way of automatically placing registers in an IC, and automatically adjusting the register placement and location based on actual timing analysis.